Two Input AND Gate Example
GENERIC(trise : delay := 10 ns;
ARCHITECTURE behav OF and2 IS
IF (a = '1' AND b = '1') THEN
ELSIF (a = '0' OR b = '0') THEN
c<= 'X' AFTER (trise+tfall)/2;
This is a simple 2 input AND gate. Note that the entity includes generics for rise time and fall time, and the two input and one output ports.
The architecture contains the “behavior” of the AND gate. A single process statement is used which executes anytime either the a or b inputs change (because they are in the process sensitivity list - see module 12). A simple if statement is used to determine what the correct output should be, and the proper delay is inserted by the AFTER clause.