Attributes Register Example (Cont.)
ARCHITECTURE behavior OF 8_bit_reg IS
IF (enable = '1') AND a'STABLE(x_setup) AND
(clk = '1') AND (clk'LAST_VALUE = '0') THEN
- The following architecture is a second and more robust attempt
- The use of 'LAST_VALUE ensures the clock is rising from a value of ‘0’
- An ELSE clause could be added to define the behavior when the requirements are not satisfied
This implementation adds a check for '0' to '1' transitions on clk by using the 'LAST_VALUE attribute on the signal clk.