The package body includes the necessary functional descriptions needed for objects declared in the package declaration
- e.g. subprogram descriptions, assignments to constants
CONSTANT My_ID : INTEGER := 2;
PROCEDURE add_bits3(SIGNAL a, b, en : IN BIT;
SIGNAL temp_result, temp_carry : OUT BIT) IS
BEGIN -- this function can return a carry
temp_result <= (a XOR b) AND en;
temp_carry <= a AND b AND en;
The package body contains the functional descriptions for the subprograms and other items declared in the corresponding package declaration.
Once a package is defined, its contents are made visible to VHDL entities and architectures via a USE clause which is analogous to the include statement of some other programming languages.