Packages and Libraries
User defined constructs declared inside architectures and entities are not visible to other VHDL components
- Scope of subprograms, user defined data types, constants, and signals is limited to the VHDL components in which they are declared
Packages and libraries provide the ability to reuse constructs in multiple entities and architectures
- Items declared in packages can be used (i.e. included) in other VHDL components
VHDL provides the package mechanism so that user-defined types, subprograms, constants, aliases, etc. can be defined once and reused in the description of multiple VHDL components.
VHDL libraries are collections of packages, entities, and architectures. The use of libraries allows the organization of the design task into any logical partition the user chooses (e.g. component libraries, package libraries to house reusable functions and type declarations).