Statements inside a process execute sequentially
ARCHITECTURE sequential OF test_mux IS
select_proc : PROCESS (x,y)
IF (select_sig = '0') THEN
ELSIF (select_sig = '1') THEN
Statements in a VHDL process are executed sequentially. A process may also include a sensitivity list which is declared immediately after the PROCESS word. The process executes when there is a transition on any of the specified signals. Alternatively, a process would include at least one wait statement to control when and where a process may suspend so that signals with pending signal assignments may assume their new values. Actually, a sensitivity list is equivalent to a wait statement at the bottom of a process which suspends execution until there is a transition on one of the signals on the sensitivity list.
The wait statement will be covered in detail in the Behavioral VHDL module.
In the example above, the sensitivity list includes signals x and y. The process can also be named; the process in the example above is named select_proc.