Concurrent Statements
Basic granularity of concurrency is the process
- Processes are executed concurrently
- Concurrent signal assignment statements are one-line processes
Mechanism for achieving concurrency :
- Processes communicate with each other via signals
- Signal assignments require delay before new value is assumed
- Simulation time advances when all active processes complete
- Effect is concurrent processing
- I.e. order in which processes are actually executed by simulator does not affect behavior
Concurrent VHDL statements include :
- Block, process, assert, signal assignment, procedure call, component instantiation