Simulation Cycle RevisitedSequential vs Concurrent Statements
VHDL is inherently a concurrent language
- All VHDL processes execute concurrently
- Concurrent signal assignment statements are actually one-line processes
VHDL statements execute sequentially within a process
Concurrent processes with sequential execution within a process offers maximum flexibility
- Supports various levels of abstraction
- Supports modeling of concurrent and sequential events as observed in real systems
In essence, VHDL is a concurrent language in that all processes execute concurrently. All VHDL execution can be seen as taking place inside processes; concurrent signal assignment statements have already been described as being equivalent to one-line processes. Within a process, however, VHDL adheres to a sequential mode of execution where statements within a process are executed in "top-to-bottom” fashion until the process suspends at a wait statement.
This simultaneous support of concurrent and sequential modes allows great flexibility in modeling systems at multiple levels of design and description abstraction.