Used for communication between VHDL components
Real, physical signals in system often mapped to VHDL signals
ALL VHDL signal assignments require either delta cycle or user-specified delay before new value is assumed
Declaration and assignment examples :
SIGNAL signal_name : type_name [:= value];
brdy <= ‘0’ AFTER 5ns, ‘1’ AFTER 10ns;
Signals are used to pass information directly between VHDL processes and entities. As has already been said, signal assignments require a delay before the signal assumes its new value. In fact, a particular signal may have a series of future values with their respective timestamps pending in the signal's waveform. The need to maintain a waveform results in a VHDL signal requiring more simulator resources than a VHDL variable.