There are four types of objects in VHDL
The scope of an object is as follows :
- Objects declared in a package are available to all VHDL descriptions that use that package
- Objects declared in an entity are available to all architectures associated with that entity
- Objects declared in an architecture are available to all statements in that architecture
- Objects declared in a process are available only within that process
VHDL 1076-1993 defines four types of objects, files, constants, variables, and signals. Simple scoping rules determine where object declarations can be used. This allows the reuse of identifiers in separate entities within the same model without risk of inadvertent errors.
For example, a signal named data could be declared within the architecture body of one component and used to interconnect its underlying subcomponents. The identifier data may also be used again in a different architecture body contained within the same model.