VHDL Data TypesSubtypes
Subtype
- Allows for user defined constraints on a data type
- e.g. a subtype based on an unconstrained VHDL type
- May include entire range of base type
- Assignments that are out of the subtype range are illegal
- Range violation detected at run time rather than compile time because only base type is checked at compile time
- Subtype declaration syntax :
- Subtype example :
SUBTYPE name IS base_type RANGE <user range>
SUBTYPE first_ten IS INTEGER RANGE 0 TO 9;
Notes:
VHDL subtypes are used to constrain defined types. Constraints take the form of range constraints or index constraints. However, a subtype may include the entire range of the base type. Assignments made to objects that are out of the subtype range generate an error at run time. The syntax and an example of a subtype declaration are shown above.