Delta Delay An Example without Delta Delay
What is the behavior of C?
NAND gate evaluated first:
AND gate evaluated first:
Notes:
For this discussion, assume that the above circuit does not specify any delays, and that there is no delta delay mechanism. In such a case, the order in which model processes (or components) are executed will affect the model outputs. Consider the example above in which there is a 1 to 0 transition at the input of the AND while the other input to the NAND gate is a constant 1. What is the behavior of C?
Note that in the case on the left where the NAND gate is evaluated before the AND gate, C can remain at its quiescent value of 0.
However, in the case on the right we see that if the AND gate is evaluated before the NAND gate, a glitch is seen at C (i.e. a static-0 hazard is observed). It is generated because the NAND gate has not yet been updated to its new value which will subsequently cause C to become 0. Therefore, C initially goes to 1 and will only go to 0 after the NAND gate drives its output to 0.
Therefore, if the order of execution is arbitrary, the behavior of the system may be unpredictable.