Inertial Delay (cont.)
Example of gate with ‘inertia’ smaller than propagation delay
- e.g. Inverter with propagation delay of 10ns which suppresses pulses shorter than 5ns
Note: the REJECT feature is new to VHDL 1076-1993
Output <= REJECT 5ns INERTIAL NOT Input AFTER 10ns;
The REJECT construct is a new feature to VHDL introduced in the VHDL 1076-1993 standard. The REJECT construct can only be used with the keyword INERTIAL to include a time parameter that specifies the input pulse width constraint.
Prior to this, a description for such a gate would have needed the use of an intermediate signal with the appropriate inertial delay followed by an assignment of this intermediate signal’s value to the actual output via a transport delay.