- All VHDL signal assignment statements prescribe an amount of time that must transpire before the signal assumes its new value
- This prescribed delay can be in one of three forms:
- Transport -- prescribes propagation delay only
- Inertial -- prescribes propagation delay and minimum input pulse width
- Delta -- the default if no delay time is explicitly specified
There are several types of delay in VHDL, and understanding of how delay works in a process is key to writing and understanding VHDL.
It bears repeating that any signal assignment in VHDL is actually a scheduling for a future value to be placed on that signal. When a signal assignment statement is executed, the signal maintains its original value until the time for the scheduled update to the new value. Any signal assignment statement will incur a delay of one of the three types listed in this slide.