VHDL provides two styles of describing component behavior
- Data Flow: concurrent signal assignment statements
- Behavioral: processes used to describe complex behavior by means of high-level language constructs
- e.g. variables, loops, if-then-else statements
A behavioral model may bear little resemblance to system implementation
- Structure not necessarily implied
A behavioral description may be relatively abstract in that specific details about a component's internal structure need not be included in the description.
The fundamental unit of behavioral description in VHDL is the process; all processes are executed concurrently with each other. In fact, the data flow modeling style is a special case of the general VHDL process mechanism in that each concurrent signal assignment statement is actually a single statement VHDL process that executes concurrently with all other processes.
Within a process, VHDL provides a rich set of constructs to allow the description of complex behavior. This includes loops, conditional statements, variables to control maintaining state information within a process (e.g. loop counters), etc.
Much more information is provided in RASSP E&F Module 12, Behavioral VHDL, which concentrates on VHDL constructs that support behavioral descriptions.