VHDL Model Components (cont.)
Fundamental unit for component behavior description is the process
- Processes may be explicitly or implicitly defined and are packaged in architectures
Primary communication mechanism is the signal
- Process executions result in new values being assigned to signals which are then accessible to other processes
- Similarly, a signal may be accessed by a process in another architecture by connecting the signal to ports in the the entities associated with the two architectures
- Example signal assignment statement :
The purpose of this slide is to provide a basic working definition for process and signal. These definitions are not intended to be comprehensive, and detail will be added throughout the presentation of this and subsequent modules.
All behavioral descriptions in VHDL are constructed using processes. Processes may be defined explicitly where complex behavior can be described in a sequential programming style, or the may be implicitly defined in concurrent signal assignment statements. Both of these mechanisms will be covered in more detail in this and subsequent modules.
The primary purpose of the process is to determine new values for signals. Signals are accessible to other processes, and, therefore, provided a mechanism for the results of one process execution to be communicated to other processes. Signals may be made accessible to processes within other VHDL architectures by connecting them to ports of the respective entities.