VHDL Model Components
A complete VHDL component description requires a VHDL entity and a VHDL architecture
- The entity defines a componentís interface
- The architecture defines a componentís function
Several alternative architectures may be developed for use with the same entity
Three areas of description for a VHDL component:
- Structural descriptions
- Behavioral descriptions
- Timing and delay descriptions
A complete VHDL description consists of an entity in which the interface signals are declared and an architecture in which the functionality of the component is described.
VHDL provides constructs and mechanisms for describing the structure of components which may me constructed from simpler sub-systems. VHDL also provides some high-level description language constructs (e.g. variables, loops, conditionals) to model complex behavior easily. Finally, the underlying timing model in VHDL supports both the concurrency and delay observed in digital electronic systems.