VHDL Design ExampleStructural Specification (cont.)
-- continuing half_adder_c description
SIGNAL xor_res : BIT; -- internal signal
-- Note that other signals are already declared in entity
A0 : and2 PORT MAP (enable, xor_res, result);
A1 : and3 PORT MAP (x, y, enable, carry);
X0 : xor2 PORT MAP (x, y, xor_res);
This second slide of the structural description shows the declaration of a local signal to be used in connecting the components together.
Finally, the body of the architecture shows the component instantiations and how they are interconnected to each other and the outside world via the attaching of signals in their PORT MAPs.