VHDL Design ExampleStructural Specification (Cont.)
ARCHITECTURE half_adder_c OF half_adder IS
PORT (in0, in1, in2 : IN BIT;
FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);
FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);
FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);
-- description is continued on next slide
Notes:
The VHDL structural description for this example is shown in this and the next slide. A number of locally defined idealized components are declared in this slide. These components are then bound to VHDL entities found in a library called gate_lib.