VHDL Design Example
Problem: Design a single bit half adder with carry and enable
- Inputs and outputs are each one bit
- When enable is high, result gets x plus y
- When enable is high, carry gets any carry of x plus y
- Outputs are zero when enable input is low
As a first example, we will consider the design a single bit adder with carry and enable functions. When the enable line is low, the adder is to place zeroes on its outputs.
This sample design sequence is directly based on an example in [Navabi93].