Gajski and Kuhnís Y Chart
VHDL allows the designer to work at various levels of abstraction. Many of the levels are shown pictorially in the Gajski/Kuhn chart. Although VHDL does not support system description at the physical/geometry level of abstraction, many design tools can take behavioral or structural VHDL and generate chip layouts.
As an illustrative example, the next few slides will show a sample VHDL design process to demonstrate how a designer can move from an algorithmic behavioral description, to a register transfer (or dataflow) description, to a gate level description. Although this chart is often referenced, this particular interpretation is found in [Smith88]. Also see
[Walker85] and [Gajski83].