Introduce basic VHDL constructs
Introduce the VHDL simulation cycle and timing model
Illustrate VHDL’s utility as a digital hardware description language
The goals of this module are to provide an introduction to the basic concepts and constructs of VHDL. VHDL is a versatile hardware description language which is useful for modeling electronic systems at various levels of design abstraction. Although most of the language will be touched on in this module, subsequent modules will cover specific areas of VHDL more thoroughly.
Specifically, areas to be covered in this module include:
-- VHDL entities, architectures, and packages
-- Concurrent and sequential modes of execution
The goal of this module is to provide a basic understanding of VHDL fundamentals in preparation for the material to be covered in the subsequent VHDL modules.