Slide 60 of 93
Signals are used to pass information directly between VHDL processes and entities. As has already been said, signal assignments require a delay before the signal assumes its new value. In fact, a particular signal may have a series of future values with their respective timestamps pending in the signal's waveform. The need to maintain a waveform results in a VHDL signal requiring more simulator resources than a VHDL variable.