Slide 17 of 93
VHDL is a powerful and versatile language and offers numerous advantages:
1) Design Methodology: VHDL supports many different design methodologies (top-down, bottom-up, delay of detail) and is very flexible in its approach to describing hardware.
2) Technology Independence: VHDL is independent of any specific technology or process. However, VHDL code can be written and then targeted for many different technologies.
3) Wide Range of Descriptions: VHDL can model hardware at various levels of design abstraction. VHDL can describe hardware from the standpoint of a "black box" to the gate level. VHDL also allows for different abstraction-level descriptions of the same component and allows the designer to mix behavioral descriptions with gate level descriptions.
4) Standard Language: The use of a standard language allows for easier documentation and the ability to run the same code in a variety of environments. Additionally, communication among designers and among design tools is enhanced by a standard language.
5) Design Management: Use of VHDL constructs, such as packages and libraries, allows common elements to be shared among members of a design group.
6) Flexible Design: VHDL can be used to model digital hardware as well as many other types of systems, including analog devices.