VHDL/Quicksim Cosimulation using QSPRO

1. What you will learn

1.1 How to compile a VHDL description for simulation with other Mentor parts.
1.2 How to create a symbol for the VHDL description.
1.3 How to instantiate this symbol in another schematic with generic Mentor parts.
1.4 How to simulate the resulting schematic with QSPro .

In order to complete this tutorial, it is expected that you already have some knowledge in the use of Design Architect to create symbols and schematics. If this is not the case, complete the applicable tutorials before attempting to proceed with this one.

2. Generate and compile the and2 component for simulation with QSPro and generate a symbol for it

In this lab, you will create a new version of the and2 component you used in lab 1 for simulation with other Mentor parts using the QSPro simulator.

2.1 To do this, you have to first modify the and2 VHDL file to use IEEE Std Logic types so that it can interface to the generic Mentor parts. Edit the and2.vhd file so that it looks like that shown below:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY and2 is

GENERIC(trise : time := 10 ns;

PORT(a : IN std_ulogic;

c : OUT std_ulogic);

END and2;

ARCHITECTURE behav OF and2 IS

ELSIF (a = '0' OR b = '0') THEN

ELSE

END IF;

END PROCESS one;

END behav;

2.2 Next, you need to compile the VHDL with a special switch that tells the compiler to generate the necessary information to create the symbol and the interface to QSPro . However, first you must map the current work library (this is required by the interface to DA, the first vmap command is necessary only once after the library is created):

>>vmap work ./work

>>vcom -qspro_syminfo and2.vhd

2.2 Start DA and generate the symbol:

>>da &

When the DA window comes up, use the menu item to bring up the Generate Symbol dialog box. Click on the Entity button in the Choose Source field. Notice how the dialog box changes the available fields. Click on the Choose Library... button in the Library Logical Name field. Choose the ["work","work"] entry in the Choose HDL Library dialog box that comes up and click OK . Click on the Choose Entity... button in the Entity Name field, select and2 in the Choose Entity box that comes up, and click OK . Click on the Choose Arch... button in the Default Architecture field, select the ["behav","HDL arch", ["hdl"]] entry in the Choose Architecture box that comes up (it should be the only entry), and click OK .

Finally, click on the Choose Shape button in the Current Shape: field and click And Gate and OK in the Choose a Symbol Shape box that comes up. The end result should be a Generate Symbol dialog box that looks like the one below.

Click OK in the Generate Symbol box. The result should be a new Symbol window appears in the DA session with an And gate symbol in it. There should be a number of properties attached to the symbol. Be very careful to not change or delete any of these properties as that may cause the simulation of the component to fail.

2.3 Add COMP and INST properties to the symbol. Make sure that nothing in the symbol is selected by using the Unselect item in the pop-up menus. Select the bottom edge of the symbol body (the AND gate) by clicking on it.Use the Properties->Add->Repeat Adding Single Properties...->Use Current Selection... item from the pop up menus to bring up the Add Property dialog box. Add a COMP property above the symbol body with a value of and2 , and an INST property with a value of ? below the symbol body as you have done before. Use the Cancel button to delete the Add Property dialog box when you are done. The result should be a symbol like the one below.

2.3 Check and save the symbol as you have done before and close the symbol window.

3. Construct a schematic for and AND-OR-INVERT (AOI) gate using the and2 component and gen_lib parts

3.1 Open a schematic sheet in DA for a component called aoi. Use the

button to bring up the Add Instance | Choose Symbol dialog box and select the and2 symbol. Add an or2 and inv component from the gen_lib library and construct a schematic like the one below. Don't forget to modify the rise and fall properties on the or2 and inv components, add INST properties to these two components, and name all of the nets.

3.2 Check and Save the aoi sheet and exit DA .

4. Simulate the aoi component with QSPro

4.1 Start the QSPro tool on the aoi component:

>>qspro -tim typ aoi &

A number of messages will be printed in the transcript window, and a OSPro(Quicksim II) and QSPro(HDL) window will appear as shown below.

QSPro uses a backplane called Flexsim to hook the ModelSim and QuickSim tools together to simulate designs which contain both VHDL components and regular Mentor Graphics ( Quicksim ) components. Within QSPro , you can use the Quicksim GUI to manipulate (trace, force, etc.) signals in the Quicksim portion of the design, and the ModelSim GUI to manipulate signals in the VHDL portion of the design. However, you can also use the Quicksim GUI to manipulate signals in the VHDL portion of the design as well, so it is easiest to simply do it there.

4.2 Make the Quicksim window active by clicking on its top edge, and open the schematic sheet. Use the Select->All->Net menu item to select all of the nets in the design and use the Add->Traces->Selected item to trace the signals. Use the Unselect->All menu item to unselect the signals.

4.3 To simply illustrate how signals can also be traced in the QHSim GUI, use the Solver->HDL menu item to bring the HDL menu to the top menu bar of the Quicksim window. Next use the Select->Area->Pin: menu item and draw a box ONLY around the and2 component so that its pins are selected. Then use the HDL->Wave... menu time to bring up the Add HDL Waves dialog box. Make sure that the Selected Objects button is selected and click OK . Notice how a ModelSim wave window appears with the /aoi_qsim/and2/a, /aoi_qsim/and2/b , and /aoi_qsim/and2/c signals (the inputs and output of the and2 VHDL component) in it.

4.3 Unselect all of the pins in the schematic and select the A input and force the following values on it: 0 at 0 ns, 1 at 160 ns, and 0 at 200 ns. Force the B input to 0 at 0 ns, and 1 at 160 ns. Force the C input to 0 at 0 ns, 1 at 80 ns, and 0 at 100 ns. Run the simulation for 240 ns. The result should be a display like the one below (with the ModelSim Wave window on top).

4.4 Exit the QSPro simulator by closing the Quicksim window.