• Use a text editor to create the behavioral VHDL description of the circuit
• Use Modelsim to simulate the behavioral VHDL description
• Use Leonardo Spectrum to synthesize the behavioral VHDL description into a gate level (structural) Verilog description
• Use Modelsim to simulate the gate level description
• Use DAIC to create and verify a schematic and symbol from the gate level description
• Use DAIC and adk_dve to prepare the design for layout

1. Create a behavioral VHDL description of the chip1 design

1.1 If not already there, move back to your tutorial directory, make a directory for lab7 then change directory into it.
>> cd egre533
>> mkdir lab7
>> cd lab7
 
1.2  Create a VHDL directory for your VHDL source and change directory into it.  (You will want to keep your source files in a separate directory to prevent accidentally overwriting them with the tools.)

>> mkdir VHDL
>> cd VHDL

 

1.3  Open a new VHDL file called adder1.vhd and using your favorite text editor and enter the following VHDL description into the file:



 
Note that the IEEE std_logic_1164 and std_logic_unsigned packages are used in this description. These packages are supported by the Leonardo Spectrum synthesis tool. For more details on the VHDL syntax supported for synthesis, see the Leonardo Spectrum HDL Synthesis Guide (/mentor/leonardo_spectrum_2004/doc/leospec_hdl.pdf).
 
1.4  Change directory back into your lab7 directory and compile the VHDL file for simulation:
 
>> cd ..
>> vlib work
>> vmap work ./work
>> vcom VHDL/adder1.vhd
 
You should see the following lines printed out with no errors:

Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Compiling entity adder1
-- Compiling architecture behavior of adder1

2. Simulate the VHDL model

The VHDL model should be functionally simulated to ensure correct operation before it is synthesized.
 
2.1  Invoke the ModelSim simulator on the adder1 design:
>> vsim adder1
 
2.2  You should see a display like the one below:



 

2.3  Use the View->Signals menu item to bring up the signals window as shown.



2.4  Use the Add->Wave->Signals in region menu item in the signals window to create a wave window.

2.5  Force values on each of the input signals (a, b, cin) using the signals window.  First select a signal as shown:



2.6  Next choose Edit->Clock from the top menu bar and fill out the dialogue box as shown.  This will make a square wave (clock) on signal a with a 50% duty cycle, 20 ns period and starting low.  Click OK.  Then add a clock force to b (40 ns period) and cin (80 ns period).



2.7  Run the simulation.  In the simulation command window type "run 80 ns" followed by the Return key as shown below.



2.8  Select the wave - default window and use the Zoom Full button to show the simulation results.  Make sure your results look similar to the one below.


 

2.9  Exit the Modelsim simulator using the File->Quit menu item in the main window.

3. Synthesize the VHDL models to ADK parts

3.1 Invoke the Leonardo Spectrum synthesis tool:
>>leonardo &
 
3.2  Select level 3 for the license because you will need level 3 to do ASIC design.



A Leonardo Spectrum window like the one below should appear.  (Leonardo may scramble your colors briefly - don't worry about it.)

Leonardo Spectrum has two operating modes: Quick Setup and Advanced Setup.  Two buttons under the top menu bar select between the modes.  See the figure below.  The buttons are under the Edit menu item; the one with the red Q is the Quick Setup button while the one with the red A is the Advanced Setup button.



3.3  Use the Tools->Variable Editor... item from the pull down menus to bring up the System Variables dialog box. Select the edifout_power_ground_style_is_net variable and set it to TRUE then left click Apply.  Use the same method to set:

max_fanout_load to 14
force_user_load_values to TRUE
vhdl_write_component_package to FALSE
vhdl_write_use_packages to library IEEE, adk; use IEEE.STD_LOGIC_1164.all; use adk.all;

Hint: You can save the command file at this point and replay it for future sessions of Leonardo to automate setting these variables.  To save it select File->Save Command File... from the top menu bar and type in a filename ("leo_vhdl", for example) then click OK.  Next time you start Leonardo, choose File->Run Script from the top menu bar then navigate to this script.

3.4  In the Quick Setup window set the Technologyto ASIC->Mentor Graphics->AMI 0.5u(typ).  Use the Open Files button to navigate to your VHDL directory then select the adder1.vhd file for input.  Your window should look like:



3.5  Toggle to Advanced Setup mode.  In the Advanced Setup window left click on the Output tab.  Then select Verilog for the output Format as shown below.  Note Leonardo will automatically set Filename to adder1.v.  Leave the other values as the defaults.



3.6  Go back to Quick Setup mode and left click the Run Flow button.  Lots of messages will scroll through the transcript window.  The final messages will be similar to those shown below for a successful synthesis.


 

3.7  Exit Leonardo by using the File->Exit menu item in the Leonardo Spectrum window.

4. Simulate the synthesized design in Verilog to be sure it functions correctly

After the VHDL model is synthesized into a gate level description, it is always a good idea to simulate the resulting design to ensure it functions correctly and the output matches the behavioral description. There are some legal, synthesizable VHDL constructs that, when synthesized, will not produce the same output as the functional description and synthesis tools have been know on rare occasions to produce incorrect results...

4.1  Map the compiled library of Verilog descriptions for the ADK parts into the proper location to compile the post-synthesis structural description (this library has been pre-compiled for you):

>> vmap adk $ADK/lib/adk_verilog

4.2  Compile the Verilog gate level (structural) description:

>> vlog adder1.v

4.3  Simulate the structural description of the adder using the precompiled gate library (command line below).  The simulator should run as before and you should see the appropriate output as before.  Note:  The gate level library does not include timing information so you will not see delays on your signals.  Also the result signal has been altered by synthesis.  This is OK.  Close ModelSim after verifying the gate level implementation.

>> vsim adder1 -L adk

5. Create a symbol and schematic for the synthesized part

After the VHDL model is synthesized, a new symbol and schematic will be generated for it.  Fortunately, DAIC will handle this automatically.
>> adk_daic &
5.1  Select File->Import Verilog... from the top menu bar.  You will see a dialogue box as shown below.



This dialogue box has one strange property - whenever you click the Netlist File(s)... button or the Output Directory... button or the Mapping File(s)... button it opens the same dialogue box.  A little confusing if you are not expecting it...

5.2  You will need to fill out all three of the top fields.  Click on the Netlist File(s)... button (or either of the other two) to show the following dialogue box.  Note the slider scroll on the bottom of this dialogue box - this box is wider than will show in the default DAIC window.



5.3  Fill in the Netlist File(s) file list by first highlighting the adder1.v file in the left file list then clicking the Add-> button for the top right file list.

5.4  Fill in the Output Directory file list by first left clicking on the BrowseUp (yellow folder with the up arrow in it) then highlighting lab7 in the left file list then left clicking the Add-> button for the middle right file list.

5.5  Fill in the Map File(s) file list by navigating to the /mentor/adk3_0/technology directory, highlighting the adk_map.vmp file in the left file list then left clicking the Add-> button for the lower right file list.  Your dialogue box should look as shown.



5.6  Click OK for this dialogue box then OK for the Import Verilog dialogue box.  DAIC will begin importing the design from your Verilog gate level netlist.  When it completes, you will see the following message in the lower left status line:



5.7  Open the schematic for adder1 by left clicking on the Schematic button in the Open portion of the session palette.  You will notice DAIC has created a component for adder1.  Double click on it, highlight the schematic and click OK.  Click OK again to open the schematic.  You schematic should look something like:



5.8  Click on the session button in the right palette.  Then click on the Symbol button in the Open portion of the schematic and open the symbol as you did the schematic.  Your symbol should look something like:



5.9  Close the symbol window.  Simulate the schematic as you have done in previous labs.  There is one difference now: your schematic has a lot of properties not normally associated with schematcis.  So when you are setting up the simulation, you should not check the Automatic check design before netlist option in the Setup Simulation Environment dialogue box.


 

5.10  Close the EZ wave viewer.  End the simulation.  Now you are in familiar territory - just click on the Prep for Layout button as before and wait for the prep to complete.  Then exit DAIC.

5.11  The final step in preparing for layout is to create the layout design viewpoint.  From the Unix command prompt enter:
 
>> adk_dve adder1


The schematic, symbol and part created use ADK ami05 library parts which have an associated layout.  You can now use IC Station to either perform schematic driven layout manually as you did in lab5 or fully automated palcement and routing as described in lab8.