Design for Actel FPGAs using VHDL and Synthesis

1. What you will learn

    1.1 How to create and compile a VHDL file for synthesis.
    1.2 How to functionally simulate the VHDL part alone and on a schematic with other parts.
    1.3 How to synthesize a VHDL description targeted towards Actel primitives.
    1.4 How to incorporate the synthesized part in a schematic with other Actel parts to generate a complete design.

2. Create a behavioral VHDL description of the chip1 design

    2.1 If not already there, move back to your tutorial directory:

      >> cd /students/<your_id>/egre427/tutorial

    2.2 Open a new VHDL file called adder1.vhd using your favorite text editor and enter the following VHDL description into the file:
      library IEEE;
      use IEEE.std_logic_1164.all;
      use IEEE.std_logic_unsigned.all;
      ENTITY adder1 is
        PORT(a : IN std_logic;
          b : IN std_logic;
          cin : IN std_logic;
          sum : OUT std_logic;
          cout : OUT std_logic);
      END adder1;
      ARCHITECTURE behavior OF adder1 IS

       
        SIGNAL result : std_logic_vector(1 downto 0);
        CONSTANT delay : time := 20 ns;
        BEGIN

         
          PROCESS(a,b,cin,result)
            VARIABLE a_temp : std_logic_vector(1 downto 0) := "00";
            VARIABLE b_temp : std_logic_vector(1 downto 0) := "00";
            VARIABLE cin_temp : std_logic_vector(1 downto 0) := "00";
            BEGIN
              a_temp(0) := a;
              b_temp(0) := b;
              cin_temp(0) := cin;
              result <= a_temp + b_temp + cin_temp;
              cout <= result(1) AFTER delay;
              sum <= result(0) AFTER delay;
          END PROCESS;
      END behavior;
       
    Note that the IEEE std_logic_1164 and std_logic_unsigned packages are used in this description. These packages are supported by the Leonardo Spectrum synthesis tool. For more details on the VHDL syntax supported for synthesis, see the Leonardo Spectrum HDL Synthesis Guide (/mentor/exemplar/doc/hdl_syn.pdf).
    2.3 Compile the VHDL file. Note that later, this VHDL model will be simulated with other Actel parts models using the QHPro tool, so the -qspro_syminfo switch will be used now to generate the necessary information:
       
      >>vlib work
      >>vmap work ./work
      >>vcom -qspro_syminfo adder1.vhd
       
    You should see the following lines printed out with no errors:
    //  ModelSim EE/VHDL 5.1h Oct  1 1998 SunOS 5.6
    //
    //  Copyright (c) Mentor Graphics Corporation, 1982-1998, All Rights Reserved.
    //                       UNPUBLISHED, LICENSED SOFTWARE.
    //            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
    //          PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
    //
    //  Copyright (c) Model Technology Incorporated 1990-1998, All Rights Reserved.
    //
    -- Loading package standard
    -- Loading package std_logic_1164
    -- Loading package std_logic_arith
    -- Loading package std_logic_unsigned
    -- Compiling entity adder1
    -- Compiling architecture behavior of adder1
     

3. Simulate the VHDL model by itself

4. Generate a symbol for the VHDL model

5. Create a 4 bit adder system that uses both the Actel full adder designed in Lab 1 and the VHDL adder created above

    5.1 With DA still open, use the Open Sheet button to open a sheet called "adder4." Use the Choose Symbol button to select the full_adder component symbol from lab 1. Instantiate two of these adders on the sheet.
     
    5.2 Use the Choose Symbol button again to select the adder1 component created above. Instantiate two of these components.
     
    5.3 Connect the four single bit adders in ripple carry configuration to implement a 4 bit adder. Add busses for the A and B inputs and the Sum output. Add a carry in and carry out signal. Note that since this schematic will be used for functional simulation only, it is not necessary to add Actel I/O pads or even portins and portouts for the system's inputs and outputs. Be sure to change the inst properties on each adder to some unique value. The resulting schematic should look like this:
     

6. Simulate the 4 bit adder with QHPro

7. Synthesize the VHDL models to Actel parts

    7.4 Click off the Run Wizard at Startup button in the INPUT FILES box and click Cancel. In the main window, click on the  button in the Quick Setup tab  and select the adder1.vhd file. Select Actel ACT1 in the Device box and select the A1020BPL84 part. Click off the Insert I/O Pads  button. Select the Technology tab and set Max Fanout to 14. Select the Outout tap and make set the Format to EDIF. Click the Run button. When the run is finished, the window should look like the one below:

8. Import the design back into the Mentor environment and generate a symbol for it

9. Generate a schematic for the synthesized design

    Invoke the Mentor Graphics schematic generator (sg) tool:
     
      >>sg &
       
    9.1 Use the File->Open Design from Viewpoint... menu item to bring up the Open Design from Viewpoint dialog box. Click on the Navigator... button and go into the "work" directory and into the adder1 component. Select the adder1 component with the  folder next to it and click OK in the Open Design from Viewpoint dialog box. A blank schematic window will appear in the sg tool window.
    9.2 Use the Setup->Symbol->Use Genlib Classification menu item to setup the symbol classifications and then use the Partition Setup... command from the pop up menus (right mouse button) to bring up the Partition Setup dialog box. Click on the Number of Sheets button, make sure the Number of Sheets item is set to 1 and click OK . Use the Generate item from the pop up menus to generate a schematic like the one below:
     

    9.3 Use the File->Save menu item to save the schematic and exit the sg tool.

10. Create a schematic for the 4 bit adder that uses the synthesized parts

11. Functionally simulate the complete Actel design