| nexsw Project Status (09/03/2008 - 16:28:01) | |||
| Project File: | nexsw.ise | Current State: | Programming File Generated |
| Module Name: | stopwatch |
|
No Errors |
| Target Device: | xc3s500e-4fg320 |
|
No Warnings |
| Product Version: | ISE 10.1.01 - Foundation |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Timing Report) |
| nexsw Partition Summary | [-] | |||
| No partition information was found. | ||||
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 83 | 9,312 | 1% | ||
| Number of 4 input LUTs | 116 | 9,312 | 1% | ||
| Logic Distribution | |||||
| Number of occupied Slices | 92 | 4,656 | 1% | ||
| Number of Slices containing only related logic | 92 | 92 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 92 | 0% | ||
| Total Number of 4 input LUTs | 166 | 9,312 | 1% | ||
| Number used as logic | 116 | ||||
| Number used as a route-thru | 50 | ||||
| Number of bonded IOBs | 19 | 232 | 8% | ||
| Number of BUFGMUXs | 1 | 24 | 4% | ||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wed Sep 3 15:40:46 2008 | 0 | 0 | 0 | |
| Translation Report | Current | Wed Sep 3 16:24:10 2008 | 0 | 0 | 0 | |
| Map Report | Current | Wed Sep 3 16:25:00 2008 | 0 | 0 | 2 Infos | |
| Place and Route Report | Current | Wed Sep 3 16:26:30 2008 | 0 | 0 | 2 Infos | |
| Static Timing Report | Current | Wed Sep 3 16:27:02 2008 | 0 | 0 | 3 Infos | |
| Bitgen Report | Current | Wed Sep 3 16:27:34 2008 | 0 | 0 | 0 | |