The Design of the VAX 4000 Model 100 and
                   MicroVAX 3100 Model 90 Desktop Systems

By Jonathan C. Crowell and David W. Maruska

1  Abstract

The MicroVAX 3100 Model 90 and VAX 4000 Model 100 systems were designed to
meet the growing demand for low-cost, high-performance desktop servers and
timesharing systems. Both systems are based on the NVAX CPU chip and a set
of VLSI support chips, which provide outstanding CPU and I/O performance.
Housed in like desktop enclosures, the two systems provide 24 times the CPU
performance of the original VAX-11/780 computer. With over 2.5 gigabytes
of disk storage and 128 megabytes of main memory, the complete base system
fits in less than one cubic foot of space. The system design was highly
leveraged from existing designs to help meet an aggressive schedule.

2  Introduction

The demand for low-cost, high-performance desktop servers and timesharing
systems is increasing rapidly. The MicroVAX 3100 Model 90 and VAX 4000
Model 100 systems were designed to meet this demand. Both systems are
based on the NVAX CPU chip and a set of very large-scale integration (VLSI)
support chips, which provide outstanding CPU and I/O performance.[1]

Each member of the MicroVAX 3100 family of systems constitutes a low-
cost, general-purpose, multiuser VAX system in an enclosure that fits
on the desktop. This enclosure supports all the required components of
a typical system, including the main memory, synchronous and asynchronous
communication lines, thick-wire and ThinWire Ethernet, and up to five small
computer system interface (SCSI)-based storage devices.

The MicroVAX 3100 Model 90 system replaces the Model 80 as the top
performer in the line; the new model has considerably more than twice
the CPU power of the previous model.[2] The Model 90 system also includes
performance enhancements to the Ethernet and SCSI adapters, as well as an
increased maximum system memory of 128 megabytes (MB). The CPU mother board
for the MicroVAX 3100 Model 90 system is called the KA50.

The VAX 4000 Model 100 system is housed in the same desktop packaging as
the MicroVAX 3100 Model 90 and provides the same base functionality. The
VAX 4000 Model 100 adds two key features found in all previous VAX 4000
systems, i.e., Digital Storage Systems Interconnect (DSSI) storage and
Q-bus expansion. The CPU mother board for the VAX 4000 Model 100 system is
called the KA52.

The KA50 and KA52 CPUs are built from a common CPU mother board design; the
base CPU mother board is configured to create either the KA50 or the KA52
product module. The DSSI and Q-bus optional hardware is added to the CPU
mother board to convert a KA50 to a KA52. Also, to provide the additional

                      Digital Technical Journal Vol. 4 No. 3 Summer 1992  1

 


 The Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


superset functionality found on the KA52 CPU, the different system read-
only memories (ROMs) are added during the manufacturing process. In this
paper, the KA50 and KA52 CPUs are referred to as the CPU mother board or
module, except where differences exist.

The system design was highly leveraged from existing designs to help meet
an aggressive schedule. This paper describes the design and implementation
of these systems.











































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3  Design Goals

The design team's primary goal was to develop a CPU mother board that would
provide at least twice the CPU performance of the MicroVAX 3100 Model 80,
while supporting all of the same I/O functionality of the previous systems.
This new system would leverage the core CPU design from the VAX 4000 Model
500 system, thus delivering the high performance of the NVAX CPU chip to
the desktop.[3]

The team set additional goals to increase system capability and
performance. These goals were to

1. Increase the maximum system memory from 72MB to 128MB

2. Provide error correction code (ECC) protection to memory using memory
   arrays that previously supported only parity

3. Increase the performance of the Ethernet adapter

4. Increase the performance of the SCSI adapter

Early in the project, the team proposed creating a second CPU design that
would have the features of the larger VAX 4000 systems. This proposal
resulted in the design of a DSSI adapter option for the CPU mother board,
as well as a Q-bus adapter to provide a means to upgrade the CPU power of
older Q-bus{-}based MicroVAX systems.

The project to design, implement, and field-test these systems was
accomplished under an aggressive schedule. Both designs were ready to
ship to customers in just over nine months from the official start of the
project.

4  System Overview

The MicroVAX 3100 Model 90 system supports the same I/O functionality as
the previous generation of systems, the MicroVAX 3100 Models 40 and 80.
The features include a SCSI storage adapter, 20 asynchronous communication
ports, two synchronous communication ports, and an Ethernet adapter.

The VAX 4000 Model 100 includes the same I/O functionality as the MicroVAX
3100 Model 90. In addition, the system provides the I/O functionality of
the larger VAX 4000 systems, that is, a high-performance DSSI storage
adapter and a Q-bus adapter port that connects to an external Q-bus
enclosure.

Both systems provide 24 times the CPU performance of a VAX-11/780 system.
The memory subsystem uses Digital's MS44 single in-line memory modules
(SIMMs) and thus provides 16MB, 32MB, 64MB, 80MB, or 128MB of main memory.

As shown in Figure 1, the system enclosure used to house both systems,
namely the BA42B, provides mounting for the CPU mother board, up to five
locations for disk and tape devices, a 166-watt power supply, and fans
for cooling the system elements. In addition, the enclosure shields the
system from radiated emissions. All I/O connections are filtered and exit

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 The Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


the enclosure through cutouts in the rear panel. The system enclosure
is compact and measures 14.99 centimeters (5.9 inches) high by 46.38
centimeters (18.26 inches) wide by 40.00 centimeters (15.75 inches) deep.

The system enclosure contains two shelves that support the mass storage
devices. In the MicroVAX 3100 Model 90, these storage locations are cabled
to support SCSI disks and tapes. The upper shelf supports three SCSI disks,
whereas the lower shelf supports two SCSI devices (any combination of
removable or 3 1/2-inch disks) with access through a door in the front
of the enclosure. In the VAX 4000 Model 100, the top shelf is configured
to support three 3 1/2-inch DSSI disks; the bottom shelf supports two SCSI
devices, as in the MicroVAX 3100 Model 90.

The VAX 4000 Model 100 DSSI support is provided by a high-performance
DSSI adapter card based on the shared-host adapter chip (SHAC), i.e., a
custom VLSI design with an integrated reduced instruction set computer
(RISC) processor.[3] The system is configured with DSSI as the primary
disk storage. The DSSI bus exits the enclosure by means of a connector on
the back panel. This expansion port can be used to connect the system to
additional DSSI devices, or to form a DSSI-based VAXcluster with a second
VAX 4000 Model 100 or any other DSSI-based system.

The Q-bus support on the VAX 4000 Model 100 is provided by the VLSI adapter
chip, i.e., the CVAX Q22-bus interface chip (CQBIC).[4] There are no Q-bus
option slots in the system enclosure. The Q-bus connects to an expansion
enclosure through a pair of connectors at the rear of the system enclosure.
Two shielded cables and the H9405 expansion module are used to connect the
Q-bus to the expansion enclosure. The near end of the Q-bus is terminated
in the system enclosure.

5  CPU Mother Board Design

The design goals presented engineering with constraints that forced
design trade-offs. Some key constraints were (1) fitting the required
functionality on a single 10-by-14-inch module; (2) designing the system to
adhere to the system power and cooling budget; and (3) minimizing changes
to the functional view of the module over previous designs, to decrease the
number of software modifications required for operating system support.

The primary way the design team minimized system development was to
leverage as much as practical from existing designs. The CPU mother
board design used components from the VAX 4000 Model 500, MicroVAX 3100
Model 80, and VAXstation 4000 Model 90 systems. Using proven design
components allowed for a shorter development cycle, smaller design teams,
and consequently, a higher-quality design, while meeting an aggressive
schedule.

The design is structured so that both CPU mother boards can be built
using the same printed wiring board (PWB). The added functionality for
the KA52 is provided by a daughter card, additional hardware and cabling,

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 Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


and different system ROMs. The shared design helped reduce the complexity
in testing and qualifying the system design.

The CPU module contains three major sections: the CPU core, the memory
subsystem, and the I/O subsystem. Figure 2 is a block diagram of the basic
CPU module for the VAX 4000 Model 100 and MicroVAX 3100 Model 90 systems.
Figure 3 is a photograph of the module, including the DSSI daughter card
option.

The CPU mother board includes a linear regulator that generates local
3.3-volt (V) current for the CPU core chip set. The voltage is stepped
down from the 5-V supply. The regulator is necessary because the 3.3-V
direct current (DC) of the system is not sufficient to meet the 3 percent
tolerance regulation or to supply the required maximum current.

                                    NOTE

   Figure 3 (CPU Mother Board) is a photograph and is unavailable.

CPU Core

The CPU core consists of three chips: the NVAX CPU chip, the NVAX data and
address lines (NDAL) memory controller (NMC) chip, and the NDAL-to-CVAX
pin (CP) bus adapter (NCA) chip. The NVAX chip directly controls the 128-
kilobyte (KB) backup cache. The core chip set is interconnected by means
of the NDAL pin bus, as shown in Figure 2. The NDAL bus is 64 bits wide,
has a 42-nanosecond (ns) cycle time, and supports pended transactions.[1]
The peak bandwidth of the NDAL bus performing 32-byte operations is 152
megabytes per second (MB/s).

NVAX CPU Chip. The NVAX CPU chip is an advanced implementation of the
VAX architecture in Digital's fourth-generation complementary metal-oxide
semiconductor (CMOS-4) technology. The NVAX device consists of 1.3 million
transistors on a die approximately 0.6 inch on a side.

The NVAX CPU chip contains the VAX CPU, a floating-point unit, and backup
cache controller logic. Some NVAX features that enable it to increase
performance are the use of a pipelined architecture, a 2KB virtual
instruction cache (VIC), a 96-entry translation buffer, an on-chip 8KB
primary cache, and an on-chip backup cache controller. The CPU cycle clock
and NDAL bus clocks are generated with an on-chip clock generator supplied
by a 286-megahertz (MHz) oscillator.

The NVAX CPU is based on a high-performance macropipelined architecture
similar to that of the VAX 9000 CPU.[1,5] The VIC allows the caching of
instructions that have already been translated to virtual addresses. Having
the backup cache controller on the chip decreases backup cache access time
because no external logic, with the resulting delays, is required.

NVAX Memory Controller Chip. The NMC is the NVAX memory controller
implemented in Digital's third-generation complementary metal-oxide
semiconductor (CMOS-3) technology.[6] The NMC consists of 148,000
transistors and is the high-speed interface to the system main memory. The

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 The Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


NMC is the arbiter for the three chips on the NDAL bus, namely, the NVAX,
the NCA, and the NMC. The NMC chip manages the array of ownership bits
that correspond to each 32-byte segment of memory. Each of these segments
corresponds to a cache line. The ownership bit indicates whether the valid
copy of the data is in memory, in the CPU write-back cache, or in an I/O
devices buffer.

The NMC has four command queues that accept read, write, and remove write
privilege transactions from the NDAL bus. Buffers hold the read data to
be returned to the node that requested the data. The NMC and the memory
subsystem provide the 95MB/s of bandwidth shared by the NVAX and the I/O
devices.

NDAL-to-CP Bus Adapter Chip. The NCA chip, also implemented in Digital's
CMOS-3 technology, is the interface from the NDAL to the CP bus.[6] The NCA
consists of 155,000 transistors and supports two CP buses. The CP bus used
on the CVAX microprocessor family is also used on many of Digital's custom
I/O adapter chips, such as the CQBIC, the SHAC, the second-generation
Ethernet controller (SGEC), and the system support chip (SSC).[3,4,7,8]
Thus, the hardware and software designs for these I/O functions could be
leveraged from previous efforts. The NCA performs direct memory access
(DMA) from the I/O devices and supports the cache consistency protocol
required for the NDAL bus.

The NCA was designed to optimize DMA traffic from CP bus devices. In the
KA50 CPU, the CP bus devices include the SGEC Ethernet adapter, the SSC,
the field erasable programmable read-only memory (FEPROM) subsystem, the
CP-to-EDAL adapter chip (CEAC), and the SCSI quadword first in, first out
(SQWF) chip. In addition, the asynchronous communication option is attached
to the CP bus. The KA52 CPU also attaches the CQBIC Q-bus adapter chip and
the SHAC DSSI host adapter chip.

Memory Subsystem

The memory subsystem is controlled by the NMC chip. The main memory is
implemented using MS44 SIMMs and low-cost gate array (LCGA) chips to
provide an interface between the NMC and the SIMMs.[9] The SIMMs are
used in groups of four to provide two interleaved banks, each with a 64-
bit data path and eight bits of ECC. This interleaving scheme increases
the bandwidth of main memory by alternating data between both banks of
memory. The ECC provides single-bit error correction and double-bit error
detection.

The individual SIMMs are available in either 4MB or 16MB variants. Since
four SIMMs form a complete functional set, sets can be 16MB or 64MB in
size. Therefore, because the system supports up to two sets of SIMMs, the
total system memory size can be either 16MB, 32MB, 64MB, 80MB, or 128MB,
depending on the combination of SIMM size and the number of sets.



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 Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


To coincide with the cache coherency scheme used in the NVAX CPU chip, the
NMC keeps track of the cache lines that have write privilege reserved by
the CPU or I/O devices. This state is stored in separate dynamic random-
access memories (DRAMs). These DRAMs interface directly to the NMC by means
of a private bus. The ownership bits are protected by ECC.

I/O Subsystem

Because the MicroVAX 3100 Model 90 was intended as an upgrade for the Model
40 and 80 systems, the I/O subsystem of the earlier systems dictated the
design of the new Model 90. In addition, the I/O subsystem of the KA52
CPU module for the VAX 4000 Model 100 supports two functions found in the
other VAX 4000 systems, the DSSI adapter and the Q-bus adapter.[9] The I/O
subsystem includes a ThinWire and thick-wire Ethernet adapter, four built-
in asynchronous terminal lines, a connector for the asynchronous option,
and the CEAC and SQWF chips.

A bus interface was incorporated in the I/O subsystem to support the DSW42
synchronous communication option, the SCSI adapter chip, and the QUART
four-port asynchronous controller chip. The CEAC and SQWF chips, which are
gate arrays designed for the VAXstation 4000 Model 90, are used to create
the EDAL bus.

Support for the SCSI bus is provided by the 53C94 SCSI adapter chip.[10]
The 53C94 chip is interfaced to the system on the EDAL bus and uses the
SQWF chip to increase its DMA performance. The SQWF chip makes it possible
to buffer data moving to the CP bus. The SCSI bus operates in synchronous
mode for high-performance storage access of 5MB/s.

The QUART gate array supplies the logic for four built-in serial ports.
The QUART, originally used on the DZQ11 Q-bus device, provides the same
software interface as that device. The third port provides modem control
functions by means of additional logic; the first, second, and fourth ports
are data leads only.

The SGEC Ethernet adapter chip was chosen because it provides higher
performance than the Ethernet adapter used on the MicroVAX 3100 Model 80.
The SGEC is the adapter chip used on all VAX 4000 systems. In addition,
this chip directly interfaces with the CP bus.

The limited size of the CPU mother board required the DSSI adapter to
be added by means of a daughter card. The Q-bus adapter chip and bus
termination are provided directly on the mother board.

6  Console and Diagnostics

The MicroVAX 3100 Models 80 and 90 differ in their console designs and
diagnostics. Because the basic CPU core of the MicroVAX 3100 Model 90 and
the VAX 4000 Model 100 systems is very similar to that of the VAX 4000
Model 500 system, the design team decided to adopt the console of the
Model 500 and add the required commands and functionality. Borrowing proven

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 The Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


designs, such as the console of another NVAX-based system, significantly
shortened the product development schedule.

One enhancement to the CPU mother board was the addition of a FEPROM
subsystem. If an update is required, the console and diagnostic code on
the CPU can be reprogrammed in the field. In contrast, previous systems
required the memories to be in sockets and the parts to be replaced in the
field. With FEPROMs, a program is loaded from any bootable device. This
program erases the FEPROMs and reprograms them with the new ROM image. This
enhancement serves as an easy mechanism for updating the ROMs in the field
to provide new features or to fix bugs that may be discovered.

On power-up, the CPU starts executing from the FEPROM memory and runs the
power-up self-test to help verify that the system is fully operational.
Upon completion of the execution of this test, the system transfers control
to the console program. Depending on the values configured in nonvolatile
memory, the console program either boots the system with the correct
parameters or stops for console input.

In earlier systems, the speed of executing from ROM could be more than
an order of magnitude slower than running from cached main memory. The
NVAX CPU chip added the virtual instruction cache, which allows the caching
of instruction stream references from I/O space. This feature greatly
increases the performance of the ROM code.

Console

The console program gains control of the CPU whenever the processor halts
or performs a restart operation such as power-up. The console provides the
following services:

1. Interface to the diagnostics that test components of the CPU and system

2. Automatic/manual bootstrap of an operating system following processor
   halts

3. An interactive command language that allows the user to examine and
   alter the state of the processor

There are minor differences between the KA50 and KA52 consoles. Largely,
these differences relate to the KA52 CPU mother board support for the DSSI
bus and the Q-bus. Although the console is similar to that found on the VAX
4000 Model 500, some new commands were implemented to provide functionality
that exists on previous MicroVAX 3100 systems. These commands include LOGIN
and SET PSWD (set password), which give support for a secure console; SET
/SHOW SCSI_ID; SHOW CONFIGURATION; SHOW ERROR; and various commands to
support a system exerciser.

On the KA52 CPU, the console supports the DSSI bus and the Q-bus with a
set of commands. These commands allow polling of the DSSI bus to determine
what devices are present and to configure the internal parameters of each
device. The system can be booted from devices on the SCSI, DSSI, or Q-bus
chips, as well as over the Ethernet port.

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 Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


Diagnostics

Diagnostics help isolate faults in the system down to the level of the
field-replaceable units. Significant effort was expended on the development
of onboard diagnostics. However, as for the console, the philosophy used in
developing these diagnostics was to leverage as much of the software design
as possible from existing designs.

With the advent of larger boot and diagnostic ROMs, the diagnostic coverage
of the power-up self-tests greatly increased, including extensive testing
of the cache, the memory, and the CPU core. These tests help assure the
customer that a failed component will be detected and reported upon
power-up. In many cases, the new tests can help isolate failures in
the individual SIMM or cache chip. This feature is used extensively in
manufacturing, as well as by field service.

During the power-up sequence, an instruction exerciser (HCORE) is run to
test the floating-point hardware. This test provides very good coverage of
the floating-point unit. In the past, HCORE has been run as a standalone
diagnostic in manufacturing before a system is shipped. The design team
for the two new desktop systems believed that this test should run on every
system power-up self-test.

The CPU core is designed to function over a wide range of environmental
conditions. Some variables of the environment are temperature, voltage,
and minimum/maximum component parameters at a given clock frequency.
Exceeding the worst-case design envelope can cause unpredictable results.
For example, to avoid problems caused by a defective main clock oscillator
that may be running too fast, the diagnostics measure the speed of the CPU
cycle clock to determine if it is within the accepted tolerance. If the
cycle is faster than the design margin dictates, an error is reported.

7  Design Tools

The design of the CPU mother board uniquely merged components from several
designs. The success of this approach relied on the use of design tools to
perform the merge and to verify the correctness of the merge.

The normal design process is to create a set of design schematics and to
verify these through simulation. Once the design is logically verified,
the layout process begins. The layout process includes the use of the SPICE
simulator to give direction to the physical layout structure and to check
the integrity of the layout.[11] After the layout is complete, the database
is fed back into logic simulation, which again verifies the correctness of
the design database.

The CPU mother board designers took a different approach. Since the
physical placement of the connector portion of the module was the same
as for the MicroVAX 3100 Model 80 module, this design element was used as
the starting point for the overall design. The database was edited using
the VAX layout system (VLS), and the only components saved were those that

                      Digital Technical Journal Vol. 4 No. 3 Summer 1992  9

 


 The Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


were to be used in the new CPU module. This procedure provided the correct
placement for all I/O connectors that exited the system enclosure.

In addition, the VAX 4000 Model 500 CPU core was used as the basis for the
CPU mother board etch layout. The Model 500 design has proven to have very
good signal integrity due to its well-thought-out circuit board layout.
To leverage Model 500 work in the layout of the CPU mother board, the
designers extracted the printed circuit board signal routing from the Model
500. This signal routing included the CPU core and cache treeing, the most
critical areas. This approach eliminated the need to model critical signal
interconnect in the design and guaranteed that the signal integrity and
connector layout would be identical to that of the proven Model 500.

Database comparison tools were used to guarantee that the schematics
matched the physical layout database. As a final step, the physical layout
database netlist was used to create a simulation model. DECSIM, Digital's
simulation tool, was used to verify the final correctness of the design
database.

8  Performance

The CPU I/O subsystems on both the MicroVAX 3100 Model 90 and the VAX 4000
Model 100 provide exceptional performance. The DSSI bus on the KA52 CPU was
tested under the VMS operating system performing single-block (512-byte)
read operations from RF35 disk drives. The read rate was measured at more
than 1,200 I/Os per second. The SCSI adapter on both CPUs was measured at
more than 500 I/Os per second for single-block reads.

The Ethernet subsystem used on both the KA50 and KA52 modules is very
efficient and has been measured transmitting 64-byte packets at a rate
of 14,789 packets per second. The measured receive rate for 64-byte packets
was 14,785 packets per second.

The performance of the CPU subsystem has traditionally been measured
using a suite of 99 benchmarks.[12] The results are scaled against the
performance of the VAX-11/780 processor, and the geometric mean is taken.
This calculation yields the VAX unit of performance (VUP) rating. The
processor VUP rating for both the KA50 and KA52 CPUs is 24 VUPs-more than
twice the performance of the MicroVAX 3100 Model 80. Table 1 presents
a summary of the performance results for the VAX 4000 Model 100 and the
MicroVAX 3100 Model 90 systems.

The performance of the system in multistream and transaction-oriented
environments was measured with TPC Benchmark A.[14] This benchmark, which
simulates a banking system, generally indicates performance in environments
characterized by concurrent CPU and I/O activity and in which more than one
program is active at any given time. The performance metric is transactions
per second (TPS). The measured performance of the VAX 4000 Model 100 is
50 TPS tpsA-local; that of the MicroVAX 3100 Model 90 is 34 TPS tpsA-
local. The difference in performance between the VAX 4000 Model 100 and

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 Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


the MicroVAX 3100 Model 90 is a result of their different disk subsystems,
i.e., the DSSI and SCSI adapter support.

9  Acknowledgements

The authors would like to thank all the designers of other products whose
logic components were used in the VAX 4000 Model 100 and MicroVAX 3100
Model 90 designs, namely, the VAXstation 4000 Model 90, VAX 4000 Model
500, and MicroVAX 3100 Model 80 teams. The authors would also like to
acknowledge the many engineers who helped design and qualify the VAX
4000 Model 100 and MicroVAX 3100 Model 90 systems on a very aggressive
schedule. Special thanks to Harold Cullison and Judy Gold (diagnostics
and console), Matt Benson and Joe Ervin (module design and debug), Cheryl
Preston (signal integrity), Dave Rouille (design verification), Colin
Brench (EMC consultant), Larry Mazzone (mechanical design), Billy Cassidy
and Walt Supinski (PWB layout), and Rita Bureau (schematics).


10  References and Note

1. G. Uhler et al., "The NVAX and NVAX+ High-performance VAX
   Microprocessors," Digital Technical Journal, vol. 4, no. 3 (Summer 1992,
   this issue): 11-23.

2. MicroVAX 3100 Models 40 and 80 Technical Information Manual, rev. 1
   (Maynard, MA: Digital Equipment Corporation, Order No. EK-A0525-TD,
   1991).

3. KA680 CPU Module Technical Manual, (Maynard, MA: Digital Equipment
   Corporation, Order No. EK-KA680-TM-001, 1992).

4. B. Maskas, "Development of the CVAX Q22-bus Interface Chip," Digital
   Technical Journal, vol. 1, no. 7 (August 1988): 129-138.

5. J. Murray, R. Hetherington, and R. Salett, "VAX Instructions That
   Illustrate the Architectural Features of the VAX 9000 CPU," Digital
   Technical Journal, vol. 2, no. 4 (Fall 1990): 25-42.

6. Jon Crowell et al., "Design of the VAX 4000 Model 400, 500, and 600
   Systems," Digital Technical Journal, vol. 4, no. 3 (Summer 1992, this
   issue): 60-72.

7. P. Rubinfeld et al., "The CVAX CPU, a CMOS VAX Microprocessor Chip,"
   ICCD Proceedings, (October 1987): 148-152.

8. G. Lidington, "Overview of the MicroVAX 3500/3600 Processor Module,"
   Digital Technical Journal, vol. 1, no. 7 (August 1988): 79-86.

9. M. Callander, Sr., L. Carlson, A. Ladd, and M. Norcross, "The VAXstation
   4000 Model 90," Digital Technical Journal, vol. 4, no. 3 (Summer 1992,
   this issue): 82-91.

10.NCR Microelectronics Products Division, NCR 53C94, 53C95, 53C96 Advanced
   Controller Data Sheet (Santa Clara, CA: NCR Corporation, 1990).

                     Digital Technical Journal Vol. 4 No. 3 Summer 1992  11

 


 The Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems


11.SPICE is a general-purpose circuit simulator program developed by
   Lawrence Nagel and Ellis Cohen of the Department of Electrical
   Engineering and Computer Sciences, University of California at Berkeley.

12.VAX Systems Performance Summary (Maynard, MA: Digital Equipment
   Corporation, Order No. EE-C0376-46, 1991).

13.SPEC: A New Perspective on Comparing System Performance, rev. 10
   (Maynard, MA: Digital Equipment Corporation, Order No. EE-EA379-46,
   1990).

14.Transaction Processing Performance Council, TPC Benchmark A Standard
   Specification (Menlo Park, CA: Waterside Associates, November 1989).

11  Biographies

Jonathan C. Crowell An engineering manager in the Entry Systems Business
Group, Jon Crowell was the project leader and system engineer on the VAX
4000 Models 100, 400, 500, and 600 and the MicroVAX 3800, 3900, and 3100
Model 90 systems. He is now working on the design of the next generation of
VAX 4000 systems. Previously, Jon worked in the Systems Integration Group
qualifying Q-bus devices and DSSI adapters and storage devices. He joined
Digital in 1986. Jon received a B.S.E.E. (1981) and an M.S.E.E. (1986) from
Northeastern University. He hold six patents and is an active member of
IEEE.

David W. Maruska Principal engineer David Maruska is a member of the Entry
Systems Business Group and is presently involved in the design of the next
generation of VAX 4000 CPUs. He was the lead designer for the KA50 and KA52
CPUs and project leader for the VAX 4000 Model 200 system, the KZQSA Q-bus-
to-SCSI adapter, and the Futurebus+ exerciser. Dave joined Digital in 1982,
after receiving a B.S. in computer engineering from Boston University.
He worked on graphics workstations for Mosaic Technologies and Raster
Technologies from 1983 to 1985 and then returned to Digital in 1986.

12  Trademarks

The following are trademarks of Digital Equipment Corporation: Digital,
KA50, KA52, MicroVAX, MS44, Q-bus, Q22-bus, ThinWire, VAX, VAX 4000,
VAX 9000, VAX-11/780, VAXcluster, VAXstation, and VMS.

SPEC, SPECfp, SPECint, and SPECmark are registered trademarks of the
Standard Performance Evaluation Cooperative.

SPICE is a trademark of the University of California at Berkeley.

TPC Benchmark and tpsA-local are trademarks of the Transaction Processing
Performance Council.



12  Digital Technical Journal Vol. 4 No. 3 Summer 1992
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